This invention relates to a thin film transistor device for driving a thin film transistor array. In particular, the driving device comprises a parallel multi-phased shift register and a multi-phased buffer combination for fast addressing select lines of a thin film transistor array, where the driving device is integrated with the array.
Amorphous silicon, (a-Si), thin film transistor technology has found numerous applications because of its low cost and processing compatibility with low temperature glass substrates which allows fabrication of large area systems. Circuits are regularly fabricated with linear dimensions in excess of 30 cm. Thin film transistors, TFTs, are widely used as pixel addressing elements in large area active matrix liquid crystal displays, and in printing and scanning bars. Printing systems based upon lonography and Electrography have also been demonstrated with a-Si. An example of a typical electrographic writing head, manufacturable by thin film fabrication techniques, is fully disclosed in U.S. Pat. No. 4,588,997 to Tuan et al. which is hereby incorporated by reference. An example of a fabrication technique is also discussed in U.S. Pat. No. 4,998,146 to Hack.
There are a variety of advantages to large area technology when it is applied to input or output devices. For many competing technologies some form of magnification is needed to scale up the system; for example laser printing or CCD scanning require optical magnification. Printing and scanning systems built in large area technology contain fewer mechanical and optical parts so the reliability can be higher. Moreover, with integrated electronic content on the input or output device, the number of interconnections may be reduced. Therefore, it would be advantageous to integrate more functionality onto a device whereby reducing the number of interconnects.
The technology for large area electronics is based in large part on an extension of crystal silicon integrated circuit technology; process modules of metal sputtering, photolithography, and chemical vapor deposition are still used. The substrate, however, can be a 32 cm.times.34 cm rectangle of Corning 7059.RTM. glass as opposed to a 15 cm.sup.2 slice from a crystalline silicon ingot. In the version of a-Si technology used for the devices in the print array there are three metal layers, a Chrome gate metal, a self aligned Chrome on N+source and drain, and an Aluminum interconnect. The TFTs are in the inverted staggered structure and a passivation layer of silicon nitride is used over the TFT channel. Polyimide is used for inter-metal isolation and for final passivation.
The most striking feature of the drive characteristics of a-Si TFTs is the low output current. These transistors have both a low mobility and a large threshold voltage (1 V to 2 V). The mobility is nearly three orders of magnitude below crystal silicon. To partly compensate for the low drive current, higher operating voltages are used. The transistors can withstand V.sub.GS (gate to source voltage) potentials up to 40 V without failure. However even with the higher drive voltage, the switching time is on the order tens of microseconds.
The slow speed of a-Si TFTs can be offset by the fact that a-Si applications lend themselves to a high degree of parallelism. For instance in an electrographic writing head, each individual writing electrode has its own separate driving circuit and in theory all of the circuits can operate in parallel for the head to function. In reality however, the number of inputs needed to drive all the circuits in parallel makes this approach impossible. To reduce the inputs to a manageable number, a simple multiplexing scheme is used. In this scheme, the a-Si circuits are grouped into segments of driver circuits which share a common data bus for data input, and each circuit in a segment has a common select line. To load the entire device with data, each select line is enabled in turn loading the data present on the bus into the segment, one segment at a time.
Besides the speed, another complication is the threshold voltage shift. This is much faster in a-Si than in crystal silicon. Rises of up to 5 V in an operational lifetime are seen and must be compensated for in the circuit design. Because of the higher threshold voltages and the slow speed of the TFTs, operating voltages are typically 15 V to 25 V. This complicates the input to large area circuits because level shifting buffers must be used. A large number of level shifters can add a significant cost to a system. It is therefore desirable to have as few inputs as possible thus reducing the number of level shifting buffers required. Such a reduction in input pads to an integrated circuit, such as disclosed herein, will decrease cost and typically increase reliability.
The example device discussed herein utilizing the present invention is a 11.84 inch, 400 driver per inch print array. The array has 32 parallel data drivers per segment, resulting in 148 segments; each being controlled by a single select line. Such a large number of inputs can drive up the cost of the array interface significantly, for reasons already discussed. There is opportunity to reduce the number of inputs even further by moving the select line drive circuitry directly into the a-Si array.
One method is to integrate into the array an a-Si serial-in/parallel-out shift register, whereby shifting a single active bit down the register enables each of the segments in turn. However, such an implementation may yield a device which is too slow for the needs of many arrays such as the electrographic writing head (e.g. 25 kHz). What is needed is an a-Si shift register for driving a one dimensional print array integrated on the same substrate as a-Si pixel drivers used for writing, which can operate at an increased speed. It would be advantageous to have a shift register design which could operate easily at an increased speed (e.g. 100 kHz) and which reduces the number of select line inputs on a device (e.g. from 148 to 9), thereby representing a significant system cost reduction. U.S. Pat. No. 4,466,020 to O'Connell shows the use of a shift register integrated on a combination read/write array. However, the shift register on that array is for loading image data, not for enabling segments of selected devices.
Another example of a device which can utilize the approach described herein is an amorphous Silicon active matrix display. For instance, for a display with 1024 columns by 1024 rows, this multi-phased shift register device can be used for the row selection. If this display is to have a frame rate of 60 Hz, this would require a line time of 16 microseconds, well within the speed of this shift register's operation. And the number of inputs for the row drivers would be reduced from 1024 to 9. As can be appreciated, the present invention could be utilized by many types of TFT arrays. Although an a-Si device is described herein, it can be appreciated that the following invention could be made from non-crystalline silicon (e.g. poly-crystalline, micro-crystalline).